v64bDhub

Access

Register

Address

Description

(RW)

v64bDhub_mem

32'h00000000

Real tcm size is 16KB Internal memory

Range

Field

Reset

Description

[31:0]

Memory

Memory

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_dHub_SemaFlexaHub_Query

32'h00004000

Used for 4ND channel Flexa handshaking operation Access address as defined above Internal memory

Range

Field

Reset

Description

[31:0]

Memory

Memory

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell0_CFG

32'h00004080

Up-to 16 semaphore cells for Flexa operation

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell1_CFG

32'h00004084

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell2_CFG

32'h00004088

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell3_CFG

32'h0000408C

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell4_CFG

32'h00004090

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell5_CFG

32'h00004094

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell6_CFG

32'h00004098

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell7_CFG

32'h0000409C

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell8_CFG

32'h000040A0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell9_CFG

32'h000040A4

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell10_CFG

32'h000040A8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell11_CFG

32'h000040AC

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell12_CFG

32'h000040B0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell13_CFG

32'h000040B4

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell14_CFG

32'h000040B8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaFlexaHub_cell15_CFG

32'h000040BC

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

[31:16]

SEG_LINE

0x0

The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored)

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_SemaFlexaHub_empty

32'h000040C0

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

All cell 'empty' status

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_SemaFlexaHub_full

32'h000040C4

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

All cell 'full' status

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_dHub_SemaHub_Query

32'h00004100

For dHub internal interrupts, also provide semaphore service for external (all channels will be opened to external to access). Channel 0 is used for dHub.HBO interrupt. Channel N+1 is used for dHub.Channel[N] interrupt. Access address as defined above Internal memory

Range

Field

Reset

Description

[31:0]

Memory

Memory

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell0_CFG

32'h00004200

Up-to 32 semaphore cells

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell0_INTR0_mask

32'h00004204

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell0_INTR1_mask

32'h00004208

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell0_INTR2_mask

32'h0000420C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell0_mask

32'h00004210

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell0_thresh

32'h00004214

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell1_CFG

32'h00004218

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell1_INTR0_mask

32'h0000421C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell1_INTR1_mask

32'h00004220

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell1_INTR2_mask

32'h00004224

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell1_mask

32'h00004228

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell1_thresh

32'h0000422C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell2_CFG

32'h00004230

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell2_INTR0_mask

32'h00004234

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell2_INTR1_mask

32'h00004238

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell2_INTR2_mask

32'h0000423C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell2_mask

32'h00004240

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell2_thresh

32'h00004244

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell3_CFG

32'h00004248

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell3_INTR0_mask

32'h0000424C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell3_INTR1_mask

32'h00004250

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell3_INTR2_mask

32'h00004254

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell3_mask

32'h00004258

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell3_thresh

32'h0000425C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell4_CFG

32'h00004260

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell4_INTR0_mask

32'h00004264

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell4_INTR1_mask

32'h00004268

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell4_INTR2_mask

32'h0000426C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell4_mask

32'h00004270

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell4_thresh

32'h00004274

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell5_CFG

32'h00004278

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell5_INTR0_mask

32'h0000427C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell5_INTR1_mask

32'h00004280

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell5_INTR2_mask

32'h00004284

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell5_mask

32'h00004288

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell5_thresh

32'h0000428C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell6_CFG

32'h00004290

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell6_INTR0_mask

32'h00004294

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell6_INTR1_mask

32'h00004298

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell6_INTR2_mask

32'h0000429C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell6_mask

32'h000042A0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell6_thresh

32'h000042A4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell7_CFG

32'h000042A8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell7_INTR0_mask

32'h000042AC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell7_INTR1_mask

32'h000042B0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell7_INTR2_mask

32'h000042B4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell7_mask

32'h000042B8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell7_thresh

32'h000042BC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell8_CFG

32'h000042C0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell8_INTR0_mask

32'h000042C4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell8_INTR1_mask

32'h000042C8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell8_INTR2_mask

32'h000042CC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell8_mask

32'h000042D0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell8_thresh

32'h000042D4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell9_CFG

32'h000042D8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell9_INTR0_mask

32'h000042DC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell9_INTR1_mask

32'h000042E0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell9_INTR2_mask

32'h000042E4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell9_mask

32'h000042E8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell9_thresh

32'h000042EC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell10_CFG

32'h000042F0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell10_INTR0_mask

32'h000042F4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell10_INTR1_mask

32'h000042F8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell10_INTR2_mask

32'h000042FC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell10_mask

32'h00004300

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell10_thresh

32'h00004304

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell11_CFG

32'h00004308

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell11_INTR0_mask

32'h0000430C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell11_INTR1_mask

32'h00004310

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell11_INTR2_mask

32'h00004314

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell11_mask

32'h00004318

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell11_thresh

32'h0000431C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell12_CFG

32'h00004320

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell12_INTR0_mask

32'h00004324

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell12_INTR1_mask

32'h00004328

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell12_INTR2_mask

32'h0000432C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell12_mask

32'h00004330

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell12_thresh

32'h00004334

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell13_CFG

32'h00004338

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell13_INTR0_mask

32'h0000433C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell13_INTR1_mask

32'h00004340

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell13_INTR2_mask

32'h00004344

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell13_mask

32'h00004348

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell13_thresh

32'h0000434C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell14_CFG

32'h00004350

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell14_INTR0_mask

32'h00004354

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell14_INTR1_mask

32'h00004358

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell14_INTR2_mask

32'h0000435C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell14_mask

32'h00004360

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell14_thresh

32'h00004364

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell15_CFG

32'h00004368

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell15_INTR0_mask

32'h0000436C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell15_INTR1_mask

32'h00004370

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell15_INTR2_mask

32'h00004374

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell15_mask

32'h00004378

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell15_thresh

32'h0000437C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell16_CFG

32'h00004380

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell16_INTR0_mask

32'h00004384

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell16_INTR1_mask

32'h00004388

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell16_INTR2_mask

32'h0000438C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell16_mask

32'h00004390

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell16_thresh

32'h00004394

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell17_CFG

32'h00004398

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell17_INTR0_mask

32'h0000439C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell17_INTR1_mask

32'h000043A0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell17_INTR2_mask

32'h000043A4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell17_mask

32'h000043A8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell17_thresh

32'h000043AC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell18_CFG

32'h000043B0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell18_INTR0_mask

32'h000043B4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell18_INTR1_mask

32'h000043B8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell18_INTR2_mask

32'h000043BC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell18_mask

32'h000043C0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell18_thresh

32'h000043C4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell19_CFG

32'h000043C8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell19_INTR0_mask

32'h000043CC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell19_INTR1_mask

32'h000043D0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell19_INTR2_mask

32'h000043D4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell19_mask

32'h000043D8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell19_thresh

32'h000043DC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell20_CFG

32'h000043E0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell20_INTR0_mask

32'h000043E4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell20_INTR1_mask

32'h000043E8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell20_INTR2_mask

32'h000043EC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell20_mask

32'h000043F0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell20_thresh

32'h000043F4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell21_CFG

32'h000043F8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell21_INTR0_mask

32'h000043FC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell21_INTR1_mask

32'h00004400

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell21_INTR2_mask

32'h00004404

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell21_mask

32'h00004408

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell21_thresh

32'h0000440C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell22_CFG

32'h00004410

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell22_INTR0_mask

32'h00004414

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell22_INTR1_mask

32'h00004418

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell22_INTR2_mask

32'h0000441C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell22_mask

32'h00004420

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell22_thresh

32'h00004424

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell23_CFG

32'h00004428

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell23_INTR0_mask

32'h0000442C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell23_INTR1_mask

32'h00004430

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell23_INTR2_mask

32'h00004434

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell23_mask

32'h00004438

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell23_thresh

32'h0000443C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell24_CFG

32'h00004440

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell24_INTR0_mask

32'h00004444

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell24_INTR1_mask

32'h00004448

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell24_INTR2_mask

32'h0000444C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell24_mask

32'h00004450

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell24_thresh

32'h00004454

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell25_CFG

32'h00004458

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell25_INTR0_mask

32'h0000445C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell25_INTR1_mask

32'h00004460

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell25_INTR2_mask

32'h00004464

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell25_mask

32'h00004468

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell25_thresh

32'h0000446C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell26_CFG

32'h00004470

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell26_INTR0_mask

32'h00004474

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell26_INTR1_mask

32'h00004478

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell26_INTR2_mask

32'h0000447C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell26_mask

32'h00004480

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell26_thresh

32'h00004484

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell27_CFG

32'h00004488

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell27_INTR0_mask

32'h0000448C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell27_INTR1_mask

32'h00004490

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell27_INTR2_mask

32'h00004494

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell27_mask

32'h00004498

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell27_thresh

32'h0000449C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell28_CFG

32'h000044A0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell28_INTR0_mask

32'h000044A4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell28_INTR1_mask

32'h000044A8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell28_INTR2_mask

32'h000044AC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell28_mask

32'h000044B0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell28_thresh

32'h000044B4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell29_CFG

32'h000044B8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell29_INTR0_mask

32'h000044BC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell29_INTR1_mask

32'h000044C0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell29_INTR2_mask

32'h000044C4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell29_mask

32'h000044C8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell29_thresh

32'h000044CC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell30_CFG

32'h000044D0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell30_INTR0_mask

32'h000044D4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell30_INTR1_mask

32'h000044D8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell30_INTR2_mask

32'h000044DC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell30_mask

32'h000044E0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell30_thresh

32'h000044E4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell31_CFG

32'h000044E8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell31_INTR0_mask

32'h000044EC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell31_INTR1_mask

32'h000044F0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell31_INTR2_mask

32'h000044F4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell31_mask

32'h000044F8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_cell31_thresh

32'h000044FC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_PUSH

32'h00004500

Range

Field

Reset

Description

[7:0]

ID

[15:8]

delta

CPU increases PCounter by delta (0 as push 256)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_SemaHub_POP

32'h00004504

Range

Field

Reset

Description

[7:0]

ID

[15:8]

delta

CPU decreases CCounter by delta (0 as pop 256)

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_SemaHub_empty

32'h00004508

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

[16:16]

ST_16i

0x0

[17:17]

ST_17i

0x0

[18:18]

ST_18i

0x0

[19:19]

ST_19i

0x0

[20:20]

ST_20i

0x0

[21:21]

ST_21i

0x0

[22:22]

ST_22i

0x0

[23:23]

ST_23i

0x0

[24:24]

ST_24i

0x0

[25:25]

ST_25i

0x0

[26:26]

ST_26i

0x0

[27:27]

ST_27i

0x0

[28:28]

ST_28i

0x0

[29:29]

ST_29i

0x0

[30:30]

ST_30i

0x0

[31:31]

ST_31i

0x0

All cell 'empty' status

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_SemaHub_full

32'h0000450C

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

[16:16]

ST_16i

0x0

[17:17]

ST_17i

0x0

[18:18]

ST_18i

0x0

[19:19]

ST_19i

0x0

[20:20]

ST_20i

0x0

[21:21]

ST_21i

0x0

[22:22]

ST_22i

0x0

[23:23]

ST_23i

0x0

[24:24]

ST_24i

0x0

[25:25]

ST_25i

0x0

[26:26]

ST_26i

0x0

[27:27]

ST_27i

0x0

[28:28]

ST_28i

0x0

[29:29]

ST_29i

0x0

[30:30]

ST_30i

0x0

[31:31]

ST_31i

0x0

All cell 'full' status

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_SemaHub_almostEmpty

32'h00004510

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

[16:16]

ST_16i

0x0

[17:17]

ST_17i

0x0

[18:18]

ST_18i

0x0

[19:19]

ST_19i

0x0

[20:20]

ST_20i

0x0

[21:21]

ST_21i

0x0

[22:22]

ST_22i

0x0

[23:23]

ST_23i

0x0

[24:24]

ST_24i

0x0

[25:25]

ST_25i

0x0

[26:26]

ST_26i

0x0

[27:27]

ST_27i

0x0

[28:28]

ST_28i

0x0

[29:29]

ST_29i

0x0

[30:30]

ST_30i

0x0

[31:31]

ST_31i

0x0

All cell 'almostEmpty' status

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_SemaHub_almostFull

32'h00004514

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

[16:16]

ST_16i

0x0

[17:17]

ST_17i

0x0

[18:18]

ST_18i

0x0

[19:19]

ST_19i

0x0

[20:20]

ST_20i

0x0

[21:21]

ST_21i

0x0

[22:22]

ST_22i

0x0

[23:23]

ST_23i

0x0

[24:24]

ST_24i

0x0

[25:25]

ST_25i

0x0

[26:26]

ST_26i

0x0

[27:27]

ST_27i

0x0

[28:28]

ST_28i

0x0

[29:29]

ST_29i

0x0

[30:30]

ST_30i

0x0

[31:31]

ST_31i

0x0

All cell 'almostFull' status

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_Query

32'h00004600

For dHub channels (command/data queues), also provide (unused) FIFO service for external. Channel 2N is used for dHub.Channel[N] command. Channel 2N+1 is used for dHub.Channel[N] data. Access address as defined above Internal memory

Range

Field

Reset

Description

[31:0]

Memory

Memory

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell0_CFG

32'h00004700

Up-to 32 semaphore cells

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell0_INTR0_mask

32'h00004704

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell0_INTR1_mask

32'h00004708

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell0_INTR2_mask

32'h0000470C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell0_mask

32'h00004710

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell0_thresh

32'h00004714

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell1_CFG

32'h00004718

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell1_INTR0_mask

32'h0000471C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell1_INTR1_mask

32'h00004720

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell1_INTR2_mask

32'h00004724

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell1_mask

32'h00004728

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell1_thresh

32'h0000472C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell2_CFG

32'h00004730

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell2_INTR0_mask

32'h00004734

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell2_INTR1_mask

32'h00004738

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell2_INTR2_mask

32'h0000473C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell2_mask

32'h00004740

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell2_thresh

32'h00004744

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell3_CFG

32'h00004748

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell3_INTR0_mask

32'h0000474C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell3_INTR1_mask

32'h00004750

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell3_INTR2_mask

32'h00004754

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell3_mask

32'h00004758

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell3_thresh

32'h0000475C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell4_CFG

32'h00004760

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell4_INTR0_mask

32'h00004764

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell4_INTR1_mask

32'h00004768

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell4_INTR2_mask

32'h0000476C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell4_mask

32'h00004770

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell4_thresh

32'h00004774

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell5_CFG

32'h00004778

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell5_INTR0_mask

32'h0000477C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell5_INTR1_mask

32'h00004780

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell5_INTR2_mask

32'h00004784

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell5_mask

32'h00004788

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell5_thresh

32'h0000478C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell6_CFG

32'h00004790

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell6_INTR0_mask

32'h00004794

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell6_INTR1_mask

32'h00004798

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell6_INTR2_mask

32'h0000479C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell6_mask

32'h000047A0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell6_thresh

32'h000047A4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell7_CFG

32'h000047A8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell7_INTR0_mask

32'h000047AC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell7_INTR1_mask

32'h000047B0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell7_INTR2_mask

32'h000047B4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell7_mask

32'h000047B8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell7_thresh

32'h000047BC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell8_CFG

32'h000047C0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell8_INTR0_mask

32'h000047C4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell8_INTR1_mask

32'h000047C8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell8_INTR2_mask

32'h000047CC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell8_mask

32'h000047D0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell8_thresh

32'h000047D4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell9_CFG

32'h000047D8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell9_INTR0_mask

32'h000047DC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell9_INTR1_mask

32'h000047E0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell9_INTR2_mask

32'h000047E4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell9_mask

32'h000047E8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell9_thresh

32'h000047EC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell10_CFG

32'h000047F0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell10_INTR0_mask

32'h000047F4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell10_INTR1_mask

32'h000047F8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell10_INTR2_mask

32'h000047FC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell10_mask

32'h00004800

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell10_thresh

32'h00004804

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell11_CFG

32'h00004808

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell11_INTR0_mask

32'h0000480C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell11_INTR1_mask

32'h00004810

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell11_INTR2_mask

32'h00004814

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell11_mask

32'h00004818

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell11_thresh

32'h0000481C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell12_CFG

32'h00004820

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell12_INTR0_mask

32'h00004824

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell12_INTR1_mask

32'h00004828

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell12_INTR2_mask

32'h0000482C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell12_mask

32'h00004830

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell12_thresh

32'h00004834

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell13_CFG

32'h00004838

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell13_INTR0_mask

32'h0000483C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell13_INTR1_mask

32'h00004840

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell13_INTR2_mask

32'h00004844

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell13_mask

32'h00004848

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell13_thresh

32'h0000484C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell14_CFG

32'h00004850

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell14_INTR0_mask

32'h00004854

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell14_INTR1_mask

32'h00004858

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell14_INTR2_mask

32'h0000485C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell14_mask

32'h00004860

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell14_thresh

32'h00004864

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell15_CFG

32'h00004868

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell15_INTR0_mask

32'h0000486C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell15_INTR1_mask

32'h00004870

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell15_INTR2_mask

32'h00004874

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell15_mask

32'h00004878

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell15_thresh

32'h0000487C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell16_CFG

32'h00004880

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell16_INTR0_mask

32'h00004884

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell16_INTR1_mask

32'h00004888

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell16_INTR2_mask

32'h0000488C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell16_mask

32'h00004890

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell16_thresh

32'h00004894

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell17_CFG

32'h00004898

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell17_INTR0_mask

32'h0000489C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell17_INTR1_mask

32'h000048A0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell17_INTR2_mask

32'h000048A4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell17_mask

32'h000048A8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell17_thresh

32'h000048AC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell18_CFG

32'h000048B0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell18_INTR0_mask

32'h000048B4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell18_INTR1_mask

32'h000048B8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell18_INTR2_mask

32'h000048BC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell18_mask

32'h000048C0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell18_thresh

32'h000048C4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell19_CFG

32'h000048C8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell19_INTR0_mask

32'h000048CC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell19_INTR1_mask

32'h000048D0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell19_INTR2_mask

32'h000048D4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell19_mask

32'h000048D8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell19_thresh

32'h000048DC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell20_CFG

32'h000048E0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell20_INTR0_mask

32'h000048E4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell20_INTR1_mask

32'h000048E8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell20_INTR2_mask

32'h000048EC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell20_mask

32'h000048F0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell20_thresh

32'h000048F4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell21_CFG

32'h000048F8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell21_INTR0_mask

32'h000048FC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell21_INTR1_mask

32'h00004900

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell21_INTR2_mask

32'h00004904

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell21_mask

32'h00004908

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell21_thresh

32'h0000490C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell22_CFG

32'h00004910

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell22_INTR0_mask

32'h00004914

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell22_INTR1_mask

32'h00004918

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell22_INTR2_mask

32'h0000491C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell22_mask

32'h00004920

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell22_thresh

32'h00004924

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell23_CFG

32'h00004928

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell23_INTR0_mask

32'h0000492C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell23_INTR1_mask

32'h00004930

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell23_INTR2_mask

32'h00004934

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell23_mask

32'h00004938

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell23_thresh

32'h0000493C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell24_CFG

32'h00004940

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell24_INTR0_mask

32'h00004944

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell24_INTR1_mask

32'h00004948

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell24_INTR2_mask

32'h0000494C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell24_mask

32'h00004950

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell24_thresh

32'h00004954

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell25_CFG

32'h00004958

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell25_INTR0_mask

32'h0000495C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell25_INTR1_mask

32'h00004960

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell25_INTR2_mask

32'h00004964

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell25_mask

32'h00004968

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell25_thresh

32'h0000496C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell26_CFG

32'h00004970

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell26_INTR0_mask

32'h00004974

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell26_INTR1_mask

32'h00004978

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell26_INTR2_mask

32'h0000497C

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell26_mask

32'h00004980

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell26_thresh

32'h00004984

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell27_CFG

32'h00004988

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell27_INTR0_mask

32'h0000498C

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell27_INTR1_mask

32'h00004990

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell27_INTR2_mask

32'h00004994

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell27_mask

32'h00004998

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell27_thresh

32'h0000499C

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell28_CFG

32'h000049A0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell28_INTR0_mask

32'h000049A4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell28_INTR1_mask

32'h000049A8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell28_INTR2_mask

32'h000049AC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell28_mask

32'h000049B0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell28_thresh

32'h000049B4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell29_CFG

32'h000049B8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell29_INTR0_mask

32'h000049BC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell29_INTR1_mask

32'h000049C0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell29_INTR2_mask

32'h000049C4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell29_mask

32'h000049C8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell29_thresh

32'h000049CC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell30_CFG

32'h000049D0

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell30_INTR0_mask

32'h000049D4

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell30_INTR1_mask

32'h000049D8

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell30_INTR2_mask

32'h000049DC

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell30_mask

32'h000049E0

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell30_thresh

32'h000049E4

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell31_CFG

32'h000049E8

Range

Field

Reset

Description

[15:0]

DEPTH

0xF

Max level of semaphore Note: write this register will trigger counter reset

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell31_INTR0_mask

32'h000049EC

Interrupt mask for 3 CPUs

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell31_INTR1_mask

32'h000049F0

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell31_INTR2_mask

32'h000049F4

Range

Field

Reset

Description

[0:0]

empty

0x0

Enable interrupt on 'empty' condition

[1:1]

full

0x0

Enable interrupt on 'full' condition

[2:2]

almostEmpty

0x0

Enable interrupt on 'almostEmpty' condition

[3:3]

almostFull

0x0

Enable interrupt on 'almostFull' condition

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell31_mask

32'h000049F8

Range

Field

Reset

Description

[0:0]

full

0x0

[1:1]

emp

0x0

When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_cell31_thresh

32'h000049FC

Range

Field

Reset

Description

[1:0]

aFull

0x0

[3:2]

aEmp

0x0

Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_PUSH

32'h00004A00

Range

Field

Reset

Description

[7:0]

ID

[15:8]

delta

CPU increases PCounter by delta (0 as push 256)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_POP

32'h00004A04

Range

Field

Reset

Description

[7:0]

ID

[15:8]

delta

CPU decreases CCounter by delta (0 as pop 256)

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_empty

32'h00004A08

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

[16:16]

ST_16i

0x0

[17:17]

ST_17i

0x0

[18:18]

ST_18i

0x0

[19:19]

ST_19i

0x0

[20:20]

ST_20i

0x0

[21:21]

ST_21i

0x0

[22:22]

ST_22i

0x0

[23:23]

ST_23i

0x0

[24:24]

ST_24i

0x0

[25:25]

ST_25i

0x0

[26:26]

ST_26i

0x0

[27:27]

ST_27i

0x0

[28:28]

ST_28i

0x0

[29:29]

ST_29i

0x0

[30:30]

ST_30i

0x0

[31:31]

ST_31i

0x0

All cell 'empty' status

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_full

32'h00004A0C

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

[16:16]

ST_16i

0x0

[17:17]

ST_17i

0x0

[18:18]

ST_18i

0x0

[19:19]

ST_19i

0x0

[20:20]

ST_20i

0x0

[21:21]

ST_21i

0x0

[22:22]

ST_22i

0x0

[23:23]

ST_23i

0x0

[24:24]

ST_24i

0x0

[25:25]

ST_25i

0x0

[26:26]

ST_26i

0x0

[27:27]

ST_27i

0x0

[28:28]

ST_28i

0x0

[29:29]

ST_29i

0x0

[30:30]

ST_30i

0x0

[31:31]

ST_31i

0x0

All cell 'full' status

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_almostEmpty

32'h00004A10

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

[16:16]

ST_16i

0x0

[17:17]

ST_17i

0x0

[18:18]

ST_18i

0x0

[19:19]

ST_19i

0x0

[20:20]

ST_20i

0x0

[21:21]

ST_21i

0x0

[22:22]

ST_22i

0x0

[23:23]

ST_23i

0x0

[24:24]

ST_24i

0x0

[25:25]

ST_25i

0x0

[26:26]

ST_26i

0x0

[27:27]

ST_27i

0x0

[28:28]

ST_28i

0x0

[29:29]

ST_29i

0x0

[30:30]

ST_30i

0x0

[31:31]

ST_31i

0x0

All cell 'almostEmpty' status

Access

Register

Address

Description

(WOC-)

v64bDhub_dHub0_dHub_HBO_FiFoCtl_almostFull

32'h00004A14

Range

Field

Reset

Description

[0:0]

ST_0i

0x0

[1:1]

ST_1i

0x0

[2:2]

ST_2i

0x0

[3:3]

ST_3i

0x0

[4:4]

ST_4i

0x0

[5:5]

ST_5i

0x0

[6:6]

ST_6i

0x0

[7:7]

ST_7i

0x0

[8:8]

ST_8i

0x0

[9:9]

ST_9i

0x0

[10:10]

ST_10i

0x0

[11:11]

ST_11i

0x0

[12:12]

ST_12i

0x0

[13:13]

ST_13i

0x0

[14:14]

ST_14i

0x0

[15:15]

ST_15i

0x0

[16:16]

ST_16i

0x0

[17:17]

ST_17i

0x0

[18:18]

ST_18i

0x0

[19:19]

ST_19i

0x0

[20:20]

ST_20i

0x0

[21:21]

ST_21i

0x0

[22:22]

ST_22i

0x0

[23:23]

ST_23i

0x0

[24:24]

ST_24i

0x0

[25:25]

ST_25i

0x0

[26:26]

ST_26i

0x0

[27:27]

ST_27i

0x0

[28:28]

ST_28i

0x0

[29:29]

ST_29i

0x0

[30:30]

ST_30i

0x0

[31:31]

ST_31i

0x0

All cell 'almostFull' status

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo0_CFG

32'h00004B00

Up-to 32 FIFO channels FiFo[N] is controlled by HBO.FiFoCtl.Channel[N]

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo0_START

32'h00004B04

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo0_CLEAR

32'h00004B08

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo0_FLUSH

32'h00004B0C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo1_CFG

32'h00004B10

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo1_START

32'h00004B14

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo1_CLEAR

32'h00004B18

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo1_FLUSH

32'h00004B1C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo2_CFG

32'h00004B20

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo2_START

32'h00004B24

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo2_CLEAR

32'h00004B28

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo2_FLUSH

32'h00004B2C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo3_CFG

32'h00004B30

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo3_START

32'h00004B34

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo3_CLEAR

32'h00004B38

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo3_FLUSH

32'h00004B3C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo4_CFG

32'h00004B40

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo4_START

32'h00004B44

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo4_CLEAR

32'h00004B48

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo4_FLUSH

32'h00004B4C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo5_CFG

32'h00004B50

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo5_START

32'h00004B54

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo5_CLEAR

32'h00004B58

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo5_FLUSH

32'h00004B5C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo6_CFG

32'h00004B60

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo6_START

32'h00004B64

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo6_CLEAR

32'h00004B68

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo6_FLUSH

32'h00004B6C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo7_CFG

32'h00004B70

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo7_START

32'h00004B74

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo7_CLEAR

32'h00004B78

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo7_FLUSH

32'h00004B7C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo8_CFG

32'h00004B80

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo8_START

32'h00004B84

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo8_CLEAR

32'h00004B88

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo8_FLUSH

32'h00004B8C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo9_CFG

32'h00004B90

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo9_START

32'h00004B94

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo9_CLEAR

32'h00004B98

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo9_FLUSH

32'h00004B9C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo10_CFG

32'h00004BA0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo10_START

32'h00004BA4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo10_CLEAR

32'h00004BA8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo10_FLUSH

32'h00004BAC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo11_CFG

32'h00004BB0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo11_START

32'h00004BB4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo11_CLEAR

32'h00004BB8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo11_FLUSH

32'h00004BBC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo12_CFG

32'h00004BC0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo12_START

32'h00004BC4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo12_CLEAR

32'h00004BC8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo12_FLUSH

32'h00004BCC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo13_CFG

32'h00004BD0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo13_START

32'h00004BD4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo13_CLEAR

32'h00004BD8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo13_FLUSH

32'h00004BDC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo14_CFG

32'h00004BE0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo14_START

32'h00004BE4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo14_CLEAR

32'h00004BE8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo14_FLUSH

32'h00004BEC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo15_CFG

32'h00004BF0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo15_START

32'h00004BF4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo15_CLEAR

32'h00004BF8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo15_FLUSH

32'h00004BFC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo16_CFG

32'h00004C00

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo16_START

32'h00004C04

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo16_CLEAR

32'h00004C08

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo16_FLUSH

32'h00004C0C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo17_CFG

32'h00004C10

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo17_START

32'h00004C14

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo17_CLEAR

32'h00004C18

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo17_FLUSH

32'h00004C1C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo18_CFG

32'h00004C20

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo18_START

32'h00004C24

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo18_CLEAR

32'h00004C28

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo18_FLUSH

32'h00004C2C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo19_CFG

32'h00004C30

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo19_START

32'h00004C34

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo19_CLEAR

32'h00004C38

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo19_FLUSH

32'h00004C3C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo20_CFG

32'h00004C40

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo20_START

32'h00004C44

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo20_CLEAR

32'h00004C48

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo20_FLUSH

32'h00004C4C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo21_CFG

32'h00004C50

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo21_START

32'h00004C54

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo21_CLEAR

32'h00004C58

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo21_FLUSH

32'h00004C5C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo22_CFG

32'h00004C60

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo22_START

32'h00004C64

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo22_CLEAR

32'h00004C68

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo22_FLUSH

32'h00004C6C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo23_CFG

32'h00004C70

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo23_START

32'h00004C74

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo23_CLEAR

32'h00004C78

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo23_FLUSH

32'h00004C7C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo24_CFG

32'h00004C80

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo24_START

32'h00004C84

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo24_CLEAR

32'h00004C88

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo24_FLUSH

32'h00004C8C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo25_CFG

32'h00004C90

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo25_START

32'h00004C94

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo25_CLEAR

32'h00004C98

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo25_FLUSH

32'h00004C9C

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo26_CFG

32'h00004CA0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo26_START

32'h00004CA4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo26_CLEAR

32'h00004CA8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo26_FLUSH

32'h00004CAC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo27_CFG

32'h00004CB0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo27_START

32'h00004CB4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo27_CLEAR

32'h00004CB8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo27_FLUSH

32'h00004CBC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo28_CFG

32'h00004CC0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo28_START

32'h00004CC4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo28_CLEAR

32'h00004CC8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo28_FLUSH

32'h00004CCC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo29_CFG

32'h00004CD0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo29_START

32'h00004CD4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo29_CLEAR

32'h00004CD8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo29_FLUSH

32'h00004CDC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo30_CFG

32'h00004CE0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo30_START

32'h00004CE4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo30_CLEAR

32'h00004CE8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo30_FLUSH

32'h00004CEC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo31_CFG

32'h00004CF0

Range

Field

Reset

Description

[19:0]

BASE

Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0;

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo31_START

32'h00004CF4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to this register will enable this channel, or 0 to this register will disable this channel.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo31_CLEAR

32'h00004CF8

Range

Field

Reset

Description

[0:0]

EN

Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH”

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_HBO_FiFo31_FLUSH

32'h00004CFC

Range

Field

Reset

Description

[0:0]

EN

No support for now

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_dHub_HBO_BUSY

32'h00004D00

Range

Field

Reset

Description

[31:0]

ST

Per channel status Indicate the clear operation status. 1: clear is in process. 0 : clear is done.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_CFG

32'h00004E00

Up-to 16 channels

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_ROB_MAP

32'h00004E04

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_AWQOS

32'h00004E08

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_ARQOS

32'h00004E0C

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_AWPARAMS

32'h00004E10

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_ARPARAMS

32'h00004E14

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_START

32'h00004E18

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_CLEAR

32'h00004E1C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl0_FLUSH

32'h00004E20

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_CFG

32'h00004E24

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_ROB_MAP

32'h00004E28

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_AWQOS

32'h00004E2C

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_ARQOS

32'h00004E30

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_AWPARAMS

32'h00004E34

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_ARPARAMS

32'h00004E38

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_START

32'h00004E3C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_CLEAR

32'h00004E40

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl1_FLUSH

32'h00004E44

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_CFG

32'h00004E48

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_ROB_MAP

32'h00004E4C

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_AWQOS

32'h00004E50

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_ARQOS

32'h00004E54

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_AWPARAMS

32'h00004E58

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_ARPARAMS

32'h00004E5C

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_START

32'h00004E60

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_CLEAR

32'h00004E64

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl2_FLUSH

32'h00004E68

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_CFG

32'h00004E6C

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_ROB_MAP

32'h00004E70

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_AWQOS

32'h00004E74

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_ARQOS

32'h00004E78

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_AWPARAMS

32'h00004E7C

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_ARPARAMS

32'h00004E80

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_START

32'h00004E84

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_CLEAR

32'h00004E88

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl3_FLUSH

32'h00004E8C

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_CFG

32'h00004E90

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_ROB_MAP

32'h00004E94

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_AWQOS

32'h00004E98

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_ARQOS

32'h00004E9C

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_AWPARAMS

32'h00004EA0

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_ARPARAMS

32'h00004EA4

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_START

32'h00004EA8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_CLEAR

32'h00004EAC

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl4_FLUSH

32'h00004EB0

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_CFG

32'h00004EB4

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_ROB_MAP

32'h00004EB8

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_AWQOS

32'h00004EBC

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_ARQOS

32'h00004EC0

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_AWPARAMS

32'h00004EC4

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_ARPARAMS

32'h00004EC8

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_START

32'h00004ECC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_CLEAR

32'h00004ED0

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl5_FLUSH

32'h00004ED4

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_CFG

32'h00004ED8

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_ROB_MAP

32'h00004EDC

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_AWQOS

32'h00004EE0

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_ARQOS

32'h00004EE4

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_AWPARAMS

32'h00004EE8

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_ARPARAMS

32'h00004EEC

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_START

32'h00004EF0

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_CLEAR

32'h00004EF4

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl6_FLUSH

32'h00004EF8

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_CFG

32'h00004EFC

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_ROB_MAP

32'h00004F00

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_AWQOS

32'h00004F04

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_ARQOS

32'h00004F08

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_AWPARAMS

32'h00004F0C

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_ARPARAMS

32'h00004F10

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_START

32'h00004F14

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_CLEAR

32'h00004F18

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl7_FLUSH

32'h00004F1C

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_CFG

32'h00004F20

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_ROB_MAP

32'h00004F24

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_AWQOS

32'h00004F28

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_ARQOS

32'h00004F2C

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_AWPARAMS

32'h00004F30

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_ARPARAMS

32'h00004F34

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_START

32'h00004F38

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_CLEAR

32'h00004F3C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl8_FLUSH

32'h00004F40

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_CFG

32'h00004F44

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_ROB_MAP

32'h00004F48

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_AWQOS

32'h00004F4C

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_ARQOS

32'h00004F50

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_AWPARAMS

32'h00004F54

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_ARPARAMS

32'h00004F58

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_START

32'h00004F5C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_CLEAR

32'h00004F60

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl9_FLUSH

32'h00004F64

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_CFG

32'h00004F68

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_ROB_MAP

32'h00004F6C

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_AWQOS

32'h00004F70

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_ARQOS

32'h00004F74

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_AWPARAMS

32'h00004F78

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_ARPARAMS

32'h00004F7C

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_START

32'h00004F80

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_CLEAR

32'h00004F84

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl10_FLUSH

32'h00004F88

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_CFG

32'h00004F8C

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_ROB_MAP

32'h00004F90

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_AWQOS

32'h00004F94

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_ARQOS

32'h00004F98

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_AWPARAMS

32'h00004F9C

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_ARPARAMS

32'h00004FA0

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_START

32'h00004FA4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_CLEAR

32'h00004FA8

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl11_FLUSH

32'h00004FAC

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_CFG

32'h00004FB0

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_ROB_MAP

32'h00004FB4

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_AWQOS

32'h00004FB8

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_ARQOS

32'h00004FBC

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_AWPARAMS

32'h00004FC0

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_ARPARAMS

32'h00004FC4

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_START

32'h00004FC8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_CLEAR

32'h00004FCC

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl12_FLUSH

32'h00004FD0

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_CFG

32'h00004FD4

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_ROB_MAP

32'h00004FD8

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_AWQOS

32'h00004FDC

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_ARQOS

32'h00004FE0

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_AWPARAMS

32'h00004FE4

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_ARPARAMS

32'h00004FE8

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_START

32'h00004FEC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_CLEAR

32'h00004FF0

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl13_FLUSH

32'h00004FF4

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_CFG

32'h00004FF8

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_ROB_MAP

32'h00004FFC

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_AWQOS

32'h00005000

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_ARQOS

32'h00005004

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_AWPARAMS

32'h00005008

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_ARPARAMS

32'h0000500C

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_START

32'h00005010

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_CLEAR

32'h00005014

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl14_FLUSH

32'h00005018

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_CFG

32'h0000501C

Range

Field

Reset

Description

[3:0]

MTU

Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB.

[4:4]

QoS

0x0

Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO

[5:5]

selfLoop

0x0

Write 1 to enable cmd looping support; 0 to turn off

[6:6]

intrCtl

0x0

0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty).

[7:7]

hScan

0x0

This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly.

[8:8]

vScan

0x0

This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_ROB_MAP

32'h00005020

Range

Field

Reset

Description

[3:0]

ID

0x0

Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_AWQOS

32'h00005024

Range

Field

Reset

Description

[3:0]

LO

0x0

AWQOS value when low priority

[7:4]

HI

0xF

AWQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_ARQOS

32'h00005028

Range

Field

Reset

Description

[3:0]

LO

0x0

ARQOS value when low priority

[7:4]

HI

0xF

ARQOS value when high priority

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_AWPARAMS

32'h0000502C

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable AWLOCK[1:0] value

[4:2]

PROT

0x0

Programmable AWPROT[2:0] value

[10:5]

USER

0x0

Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd

[13:11]

CACHE

0x0

Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware

[14:14]

USER_HI_EN

0x0

0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_ARPARAMS

32'h00005030

Range

Field

Reset

Description

[1:0]

LOCK

0x0

Programmable ARLOCK[1:0] value

[4:2]

PROT

0x0

Programmable ARPROT[2:0] value

[10:5]

USER

0x0

Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd

[14:11]

CACHE

0x0

Programmable AWCACHE[3:0] value

[15:15]

USER_HI_EN

0x0

0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_START

32'h00005034

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_CLEAR

32'h00005038

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the channel controller state

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_dHub_channelCtl15_FLUSH

32'h0000503C

Range

Field

Reset

Description

[0:0]

EN

Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_dHub_BUSY

32'h00005040

Range

Field

Reset

Description

[15:0]

ST

Per channel status 0: no ongoing command is being processed, and no flushing is taking place 1: channel controller is busy

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_dHub_PENDING

32'h00005044

Range

Field

Reset

Description

[15:0]

ST

Per channel status 0: Response queue is empty, meaning no outstanding AXI transactions 1: there exist some outstanding AXI transactions

Access

Register

Address

Description

(RW-)

v64bDhub_dHub0_dHub_busRstEn

32'h00005048

Range

Field

Reset

Description

[0:0]

reg

0x0

Write one to this register will trigger gate-keeper to take over the AXI bus.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_dHub_busRstDone

32'h0000504C

Range

Field

Reset

Description

[0:0]

reg

0x1

After gate-keeper take over the AXI bus, it will assert this bit once there is no outstanding transactions on AXI bus.

Access

Register

Address

Description

(P)

v64bDhub_dHub0_dHub_flowCtl

32'h00005050

Range

Field

Reset

Description

[7:0]

rAlpha

0x0

[15:8]

wAlpha

0x0

Flow control parameter for read and write axi master. clkCnt=(alpha*bstLen) > >4. This # of clock cycles will be blocked for the axi master after an axi command with the burst length of “bstLen”. When set alpha to be 0, the master will never be blocked.

Access

Register

Address

Description

(P)

v64bDhub_dHub0_dHub_axiCmdCol

32'h00005054

Range

Field

Reset

Description

[15:0]

rCnt

0x0

[31:16]

wCnt

0x0

Axi command collection. The counter value indicate read/write do the command collection for # of clock cycles, start from the first command pushed to an empty command Q. Here are the conditions that will trigger the Axi master to send out command. Cmd Q full or the counter count down to “0” from the programmed value. Set the counter to 0 will disable the command collection.

Access

Register

Address

Description

(P)

v64bDhub_dHub0_dHub_axiMultiIdEn

32'h00005058

Range

Field

Reset

Description

[0:0]

reg

0x0

When 0, the read channel will have AXI_ID = ROB_ID. ROB_ID is dependent on which ROB the read channel is mapped to in dHubChannel.ROB_MAP.ID write channel will have AXI_ID = 0. Write one to this register to enable multi-ID support. Multi-ID when enabled will issue AXI IDs = channel number for each AXI transaction. Note: If set to 1, the read slave return must never interleave RIDs. If slave return interleaves RID, this bit must never be set to 1. end dHubReg

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D0_MEM

32'h00005100

Up-to 16 2D channels. 2D Channel[N] is connected to dHub.Channel[N] command queue, that is, dHub.HBO.Channel[2N] Note: Number of 2D channels could be less than dHub channels (rest of are 1D only)

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D0_DESC

32'h00005104

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D0_START

32'h00005108

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D0_CLEAR

32'h0000510C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D0_HDR0_DESC

32'h00005110

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D0_HDR1_DESC

32'h00005114

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D0_HDR2_DESC

32'h00005118

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D0_HDR3_DESC

32'h0000511C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D1_MEM

32'h00005120

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D1_DESC

32'h00005124

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D1_START

32'h00005128

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D1_CLEAR

32'h0000512C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D1_HDR0_DESC

32'h00005130

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D1_HDR1_DESC

32'h00005134

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D1_HDR2_DESC

32'h00005138

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D1_HDR3_DESC

32'h0000513C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D2_MEM

32'h00005140

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D2_DESC

32'h00005144

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D2_START

32'h00005148

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D2_CLEAR

32'h0000514C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D2_HDR0_DESC

32'h00005150

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D2_HDR1_DESC

32'h00005154

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D2_HDR2_DESC

32'h00005158

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D2_HDR3_DESC

32'h0000515C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D3_MEM

32'h00005160

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D3_DESC

32'h00005164

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D3_START

32'h00005168

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D3_CLEAR

32'h0000516C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D3_HDR0_DESC

32'h00005170

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D3_HDR1_DESC

32'h00005174

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D3_HDR2_DESC

32'h00005178

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D3_HDR3_DESC

32'h0000517C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D4_MEM

32'h00005180

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D4_DESC

32'h00005184

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D4_START

32'h00005188

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D4_CLEAR

32'h0000518C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D4_HDR0_DESC

32'h00005190

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D4_HDR1_DESC

32'h00005194

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D4_HDR2_DESC

32'h00005198

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D4_HDR3_DESC

32'h0000519C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D5_MEM

32'h000051A0

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D5_DESC

32'h000051A4

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D5_START

32'h000051A8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D5_CLEAR

32'h000051AC

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D5_HDR0_DESC

32'h000051B0

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D5_HDR1_DESC

32'h000051B4

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D5_HDR2_DESC

32'h000051B8

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D5_HDR3_DESC

32'h000051BC

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D6_MEM

32'h000051C0

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D6_DESC

32'h000051C4

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D6_START

32'h000051C8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D6_CLEAR

32'h000051CC

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D6_HDR0_DESC

32'h000051D0

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D6_HDR1_DESC

32'h000051D4

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D6_HDR2_DESC

32'h000051D8

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D6_HDR3_DESC

32'h000051DC

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D7_MEM

32'h000051E0

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D7_DESC

32'h000051E4

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D7_START

32'h000051E8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D7_CLEAR

32'h000051EC

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D7_HDR0_DESC

32'h000051F0

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D7_HDR1_DESC

32'h000051F4

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D7_HDR2_DESC

32'h000051F8

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D7_HDR3_DESC

32'h000051FC

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D8_MEM

32'h00005200

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D8_DESC

32'h00005204

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D8_START

32'h00005208

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D8_CLEAR

32'h0000520C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D8_HDR0_DESC

32'h00005210

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D8_HDR1_DESC

32'h00005214

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D8_HDR2_DESC

32'h00005218

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D8_HDR3_DESC

32'h0000521C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D9_MEM

32'h00005220

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D9_DESC

32'h00005224

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D9_START

32'h00005228

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D9_CLEAR

32'h0000522C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D9_HDR0_DESC

32'h00005230

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D9_HDR1_DESC

32'h00005234

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D9_HDR2_DESC

32'h00005238

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D9_HDR3_DESC

32'h0000523C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D10_MEM

32'h00005240

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D10_DESC

32'h00005244

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D10_START

32'h00005248

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D10_CLEAR

32'h0000524C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D10_HDR0_DESC

32'h00005250

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D10_HDR1_DESC

32'h00005254

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D10_HDR2_DESC

32'h00005258

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D10_HDR3_DESC

32'h0000525C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D11_MEM

32'h00005260

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D11_DESC

32'h00005264

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D11_START

32'h00005268

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D11_CLEAR

32'h0000526C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D11_HDR0_DESC

32'h00005270

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D11_HDR1_DESC

32'h00005274

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D11_HDR2_DESC

32'h00005278

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D11_HDR3_DESC

32'h0000527C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D12_MEM

32'h00005280

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D12_DESC

32'h00005284

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D12_START

32'h00005288

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D12_CLEAR

32'h0000528C

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D12_HDR0_DESC

32'h00005290

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D12_HDR1_DESC

32'h00005294

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D12_HDR2_DESC

32'h00005298

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D12_HDR3_DESC

32'h0000529C

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D13_MEM

32'h000052A0

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D13_DESC

32'h000052A4

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D13_START

32'h000052A8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D13_CLEAR

32'h000052AC

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D13_HDR0_DESC

32'h000052B0

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D13_HDR1_DESC

32'h000052B4

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D13_HDR2_DESC

32'h000052B8

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D13_HDR3_DESC

32'h000052BC

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D14_MEM

32'h000052C0

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D14_DESC

32'h000052C4

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D14_START

32'h000052C8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D14_CLEAR

32'h000052CC

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D14_HDR0_DESC

32'h000052D0

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D14_HDR1_DESC

32'h000052D4

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D14_HDR2_DESC

32'h000052D8

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D14_HDR3_DESC

32'h000052DC

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D15_MEM

32'h000052E0

Range

Field

Reset

Description

[31:0]

addr

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D15_DESC

32'h000052E4

Range

Field

Reset

Description

[15:0]

stride

Line stride size in bytes

[28:16]

numLine

Number of lines in buffer. Size of 0 is forbidden.

[30:29]

hdrLoop

Size of line-loop for choosing dHubCmdHDR 0 is treated as 4

[31:31]

interrupt

1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D15_START

32'h000052E8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel; 0 to pause the channel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D15_CLEAR

32'h000052EC

Range

Field

Reset

Description

[0:0]

EN

Write anything to reset the 2D engine.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D15_HDR0_DESC

32'h000052F0

Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D15_HDR1_DESC

32'h000052F4

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D15_HDR2_DESC

32'h000052F8

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2D15_HDR3_DESC

32'h000052FC

Range

Field

Reset

Description

[15:0]

size

amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden.

[16:16]

sizeMTU

0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition)

[17:17]

semOpMTU

0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level

[22:18]

chkSemId

ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled

[27:23]

updSemId

ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled

[28:28]

interrupt

1: raise interrupt upon command finish

[29:29]

ovrdQos

0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd

[30:30]

disSem

Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]}

[31:31]

qosSel

0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND0_MEM

32'h00005300

Up-to 16 2ND channels. 2ND Channel[N] is connected to dHub.Channel[N] command queue, that is, dHub.HBO.Channel[2N] Note: 2ND engines are instantiated in the same way as the old 2D engine. It is allowed to have multiple 1D, 2D, 2ND and 4ND channels in a dHub. Restriction is each channel can only have one type.

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND0_DESC

32'h00005304

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND0_DESC_1D_ST

32'h00005308

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND0_DESC_1D_SZ

32'h0000530C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND0_DESC_2D_ST

32'h00005310

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND0_DESC_2D_SZ

32'h00005314

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND0_START

32'h00005318

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND0_CLEAR

32'h0000531C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND1_MEM

32'h00005320

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND1_DESC

32'h00005324

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND1_DESC_1D_ST

32'h00005328

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND1_DESC_1D_SZ

32'h0000532C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND1_DESC_2D_ST

32'h00005330

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND1_DESC_2D_SZ

32'h00005334

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND1_START

32'h00005338

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND1_CLEAR

32'h0000533C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND2_MEM

32'h00005340

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND2_DESC

32'h00005344

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND2_DESC_1D_ST

32'h00005348

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND2_DESC_1D_SZ

32'h0000534C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND2_DESC_2D_ST

32'h00005350

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND2_DESC_2D_SZ

32'h00005354

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND2_START

32'h00005358

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND2_CLEAR

32'h0000535C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND3_MEM

32'h00005360

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND3_DESC

32'h00005364

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND3_DESC_1D_ST

32'h00005368

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND3_DESC_1D_SZ

32'h0000536C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND3_DESC_2D_ST

32'h00005370

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND3_DESC_2D_SZ

32'h00005374

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND3_START

32'h00005378

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND3_CLEAR

32'h0000537C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND4_MEM

32'h00005380

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND4_DESC

32'h00005384

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND4_DESC_1D_ST

32'h00005388

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND4_DESC_1D_SZ

32'h0000538C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND4_DESC_2D_ST

32'h00005390

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND4_DESC_2D_SZ

32'h00005394

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND4_START

32'h00005398

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND4_CLEAR

32'h0000539C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND5_MEM

32'h000053A0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND5_DESC

32'h000053A4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND5_DESC_1D_ST

32'h000053A8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND5_DESC_1D_SZ

32'h000053AC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND5_DESC_2D_ST

32'h000053B0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND5_DESC_2D_SZ

32'h000053B4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND5_START

32'h000053B8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND5_CLEAR

32'h000053BC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND6_MEM

32'h000053C0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND6_DESC

32'h000053C4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND6_DESC_1D_ST

32'h000053C8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND6_DESC_1D_SZ

32'h000053CC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND6_DESC_2D_ST

32'h000053D0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND6_DESC_2D_SZ

32'h000053D4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND6_START

32'h000053D8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND6_CLEAR

32'h000053DC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND7_MEM

32'h000053E0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND7_DESC

32'h000053E4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND7_DESC_1D_ST

32'h000053E8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND7_DESC_1D_SZ

32'h000053EC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND7_DESC_2D_ST

32'h000053F0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND7_DESC_2D_SZ

32'h000053F4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND7_START

32'h000053F8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND7_CLEAR

32'h000053FC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND8_MEM

32'h00005400

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND8_DESC

32'h00005404

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND8_DESC_1D_ST

32'h00005408

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND8_DESC_1D_SZ

32'h0000540C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND8_DESC_2D_ST

32'h00005410

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND8_DESC_2D_SZ

32'h00005414

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND8_START

32'h00005418

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND8_CLEAR

32'h0000541C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND9_MEM

32'h00005420

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND9_DESC

32'h00005424

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND9_DESC_1D_ST

32'h00005428

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND9_DESC_1D_SZ

32'h0000542C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND9_DESC_2D_ST

32'h00005430

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND9_DESC_2D_SZ

32'h00005434

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND9_START

32'h00005438

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND9_CLEAR

32'h0000543C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND10_MEM

32'h00005440

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND10_DESC

32'h00005444

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND10_DESC_1D_ST

32'h00005448

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND10_DESC_1D_SZ

32'h0000544C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND10_DESC_2D_ST

32'h00005450

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND10_DESC_2D_SZ

32'h00005454

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND10_START

32'h00005458

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND10_CLEAR

32'h0000545C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND11_MEM

32'h00005460

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND11_DESC

32'h00005464

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND11_DESC_1D_ST

32'h00005468

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND11_DESC_1D_SZ

32'h0000546C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND11_DESC_2D_ST

32'h00005470

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND11_DESC_2D_SZ

32'h00005474

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND11_START

32'h00005478

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND11_CLEAR

32'h0000547C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND12_MEM

32'h00005480

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND12_DESC

32'h00005484

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND12_DESC_1D_ST

32'h00005488

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND12_DESC_1D_SZ

32'h0000548C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND12_DESC_2D_ST

32'h00005490

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND12_DESC_2D_SZ

32'h00005494

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND12_START

32'h00005498

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND12_CLEAR

32'h0000549C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND13_MEM

32'h000054A0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND13_DESC

32'h000054A4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND13_DESC_1D_ST

32'h000054A8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND13_DESC_1D_SZ

32'h000054AC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND13_DESC_2D_ST

32'h000054B0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND13_DESC_2D_SZ

32'h000054B4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND13_START

32'h000054B8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND13_CLEAR

32'h000054BC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND14_MEM

32'h000054C0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND14_DESC

32'h000054C4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND14_DESC_1D_ST

32'h000054C8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND14_DESC_1D_SZ

32'h000054CC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND14_DESC_2D_ST

32'h000054D0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND14_DESC_2D_SZ

32'h000054D4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND14_START

32'h000054D8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND14_CLEAR

32'h000054DC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND15_MEM

32'h000054E0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 2D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND15_DESC

32'h000054E4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine

[26:26]

interrupt

0x0

1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND15_DESC_1D_ST

32'h000054E8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND15_DESC_1D_SZ

32'h000054EC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND15_DESC_2D_ST

32'h000054F0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND15_DESC_2D_SZ

32'h000054F4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND15_START

32'h000054F8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 2D buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd2ND15_CLEAR

32'h000054FC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 2D engine. end dHubCmd2ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_MEM

32'h00005500

Up-to 16 4ND channels. 4ND Channel[N] is connected to dHub.Channel[N] command queue, that is, dHub.HBO.Channel[2N] Note: 4ND engines are instantiated in the same way as the old 2D engine. It is allowed to have multiple 1D, 2D, 2ND and 4ND channels in a dHub. Restriction is each channel can only have one type.

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC

32'h00005504

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC_1D_ST

32'h00005508

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC_1D_SZ

32'h0000550C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC_2D_ST

32'h00005510

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC_2D_SZ

32'h00005514

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC_3D_ST

32'h00005518

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC_3D_SZ

32'h0000551C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC_4D_ST

32'h00005520

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_DESC_4D_SZ

32'h00005524

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_START

32'h00005528

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND0_CLEAR

32'h0000552C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND0_FLEXA

32'h00005530

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND0_FLEXA_INTR_STA

32'h00005534

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND0_FLEXA_INTR_MSK

32'h00005538

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_MEM

32'h0000553C

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC

32'h00005540

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC_1D_ST

32'h00005544

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC_1D_SZ

32'h00005548

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC_2D_ST

32'h0000554C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC_2D_SZ

32'h00005550

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC_3D_ST

32'h00005554

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC_3D_SZ

32'h00005558

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC_4D_ST

32'h0000555C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_DESC_4D_SZ

32'h00005560

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_START

32'h00005564

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND1_CLEAR

32'h00005568

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND1_FLEXA

32'h0000556C

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND1_FLEXA_INTR_STA

32'h00005570

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND1_FLEXA_INTR_MSK

32'h00005574

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_MEM

32'h00005578

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC

32'h0000557C

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC_1D_ST

32'h00005580

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC_1D_SZ

32'h00005584

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC_2D_ST

32'h00005588

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC_2D_SZ

32'h0000558C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC_3D_ST

32'h00005590

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC_3D_SZ

32'h00005594

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC_4D_ST

32'h00005598

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_DESC_4D_SZ

32'h0000559C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_START

32'h000055A0

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND2_CLEAR

32'h000055A4

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND2_FLEXA

32'h000055A8

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND2_FLEXA_INTR_STA

32'h000055AC

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND2_FLEXA_INTR_MSK

32'h000055B0

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_MEM

32'h000055B4

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC

32'h000055B8

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC_1D_ST

32'h000055BC

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC_1D_SZ

32'h000055C0

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC_2D_ST

32'h000055C4

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC_2D_SZ

32'h000055C8

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC_3D_ST

32'h000055CC

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC_3D_SZ

32'h000055D0

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC_4D_ST

32'h000055D4

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_DESC_4D_SZ

32'h000055D8

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_START

32'h000055DC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND3_CLEAR

32'h000055E0

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND3_FLEXA

32'h000055E4

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND3_FLEXA_INTR_STA

32'h000055E8

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND3_FLEXA_INTR_MSK

32'h000055EC

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_MEM

32'h000055F0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC

32'h000055F4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC_1D_ST

32'h000055F8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC_1D_SZ

32'h000055FC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC_2D_ST

32'h00005600

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC_2D_SZ

32'h00005604

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC_3D_ST

32'h00005608

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC_3D_SZ

32'h0000560C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC_4D_ST

32'h00005610

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_DESC_4D_SZ

32'h00005614

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_START

32'h00005618

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND4_CLEAR

32'h0000561C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND4_FLEXA

32'h00005620

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND4_FLEXA_INTR_STA

32'h00005624

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND4_FLEXA_INTR_MSK

32'h00005628

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_MEM

32'h0000562C

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC

32'h00005630

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC_1D_ST

32'h00005634

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC_1D_SZ

32'h00005638

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC_2D_ST

32'h0000563C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC_2D_SZ

32'h00005640

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC_3D_ST

32'h00005644

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC_3D_SZ

32'h00005648

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC_4D_ST

32'h0000564C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_DESC_4D_SZ

32'h00005650

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_START

32'h00005654

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND5_CLEAR

32'h00005658

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND5_FLEXA

32'h0000565C

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND5_FLEXA_INTR_STA

32'h00005660

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND5_FLEXA_INTR_MSK

32'h00005664

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_MEM

32'h00005668

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC

32'h0000566C

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC_1D_ST

32'h00005670

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC_1D_SZ

32'h00005674

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC_2D_ST

32'h00005678

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC_2D_SZ

32'h0000567C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC_3D_ST

32'h00005680

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC_3D_SZ

32'h00005684

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC_4D_ST

32'h00005688

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_DESC_4D_SZ

32'h0000568C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_START

32'h00005690

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND6_CLEAR

32'h00005694

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND6_FLEXA

32'h00005698

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND6_FLEXA_INTR_STA

32'h0000569C

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND6_FLEXA_INTR_MSK

32'h000056A0

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_MEM

32'h000056A4

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC

32'h000056A8

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC_1D_ST

32'h000056AC

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC_1D_SZ

32'h000056B0

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC_2D_ST

32'h000056B4

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC_2D_SZ

32'h000056B8

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC_3D_ST

32'h000056BC

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC_3D_SZ

32'h000056C0

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC_4D_ST

32'h000056C4

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_DESC_4D_SZ

32'h000056C8

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_START

32'h000056CC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND7_CLEAR

32'h000056D0

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND7_FLEXA

32'h000056D4

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND7_FLEXA_INTR_STA

32'h000056D8

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND7_FLEXA_INTR_MSK

32'h000056DC

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_MEM

32'h000056E0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC

32'h000056E4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC_1D_ST

32'h000056E8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC_1D_SZ

32'h000056EC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC_2D_ST

32'h000056F0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC_2D_SZ

32'h000056F4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC_3D_ST

32'h000056F8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC_3D_SZ

32'h000056FC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC_4D_ST

32'h00005700

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_DESC_4D_SZ

32'h00005704

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_START

32'h00005708

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND8_CLEAR

32'h0000570C

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND8_FLEXA

32'h00005710

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND8_FLEXA_INTR_STA

32'h00005714

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND8_FLEXA_INTR_MSK

32'h00005718

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_MEM

32'h0000571C

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC

32'h00005720

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC_1D_ST

32'h00005724

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC_1D_SZ

32'h00005728

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC_2D_ST

32'h0000572C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC_2D_SZ

32'h00005730

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC_3D_ST

32'h00005734

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC_3D_SZ

32'h00005738

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC_4D_ST

32'h0000573C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_DESC_4D_SZ

32'h00005740

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_START

32'h00005744

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND9_CLEAR

32'h00005748

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND9_FLEXA

32'h0000574C

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND9_FLEXA_INTR_STA

32'h00005750

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND9_FLEXA_INTR_MSK

32'h00005754

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_MEM

32'h00005758

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC

32'h0000575C

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC_1D_ST

32'h00005760

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC_1D_SZ

32'h00005764

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC_2D_ST

32'h00005768

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC_2D_SZ

32'h0000576C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC_3D_ST

32'h00005770

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC_3D_SZ

32'h00005774

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC_4D_ST

32'h00005778

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_DESC_4D_SZ

32'h0000577C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_START

32'h00005780

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND10_CLEAR

32'h00005784

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND10_FLEXA

32'h00005788

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND10_FLEXA_INTR_STA

32'h0000578C

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND10_FLEXA_INTR_MSK

32'h00005790

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_MEM

32'h00005794

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC

32'h00005798

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC_1D_ST

32'h0000579C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC_1D_SZ

32'h000057A0

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC_2D_ST

32'h000057A4

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC_2D_SZ

32'h000057A8

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC_3D_ST

32'h000057AC

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC_3D_SZ

32'h000057B0

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC_4D_ST

32'h000057B4

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_DESC_4D_SZ

32'h000057B8

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_START

32'h000057BC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND11_CLEAR

32'h000057C0

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND11_FLEXA

32'h000057C4

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND11_FLEXA_INTR_STA

32'h000057C8

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND11_FLEXA_INTR_MSK

32'h000057CC

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_MEM

32'h000057D0

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC

32'h000057D4

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC_1D_ST

32'h000057D8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC_1D_SZ

32'h000057DC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC_2D_ST

32'h000057E0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC_2D_SZ

32'h000057E4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC_3D_ST

32'h000057E8

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC_3D_SZ

32'h000057EC

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC_4D_ST

32'h000057F0

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_DESC_4D_SZ

32'h000057F4

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_START

32'h000057F8

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND12_CLEAR

32'h000057FC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND12_FLEXA

32'h00005800

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND12_FLEXA_INTR_STA

32'h00005804

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND12_FLEXA_INTR_MSK

32'h00005808

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_MEM

32'h0000580C

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC

32'h00005810

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC_1D_ST

32'h00005814

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC_1D_SZ

32'h00005818

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC_2D_ST

32'h0000581C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC_2D_SZ

32'h00005820

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC_3D_ST

32'h00005824

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC_3D_SZ

32'h00005828

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC_4D_ST

32'h0000582C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_DESC_4D_SZ

32'h00005830

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_START

32'h00005834

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND13_CLEAR

32'h00005838

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND13_FLEXA

32'h0000583C

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND13_FLEXA_INTR_STA

32'h00005840

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND13_FLEXA_INTR_MSK

32'h00005844

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_MEM

32'h00005848

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC

32'h0000584C

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC_1D_ST

32'h00005850

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC_1D_SZ

32'h00005854

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC_2D_ST

32'h00005858

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC_2D_SZ

32'h0000585C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC_3D_ST

32'h00005860

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC_3D_SZ

32'h00005864

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC_4D_ST

32'h00005868

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_DESC_4D_SZ

32'h0000586C

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_START

32'h00005870

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND14_CLEAR

32'h00005874

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND14_FLEXA

32'h00005878

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND14_FLEXA_INTR_STA

32'h0000587C

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND14_FLEXA_INTR_MSK

32'h00005880

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_MEM

32'h00005884

Range

Field

Reset

Description

[31:0]

addr

0x0

DRAM data address of the 4D buffer, in bytes.

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC

32'h00005888

Range

Field

Reset

Description

[15:0]

burst

0x1

Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size

[20:16]

chkSemId

0x0

0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[25:21]

updSemId

0x0

0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID

[26:26]

interrupt

0x0

1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command.

[27:27]

ovrdQos

0x0

Follows the definition of dHubCmdHDR.ovrdQos

[28:28]

disSem

0x0

Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0

[29:29]

qosSel

0x0

Follows the definition of dHubCmdHdr.qosSel

[31:30]

mode

0x0

0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC_1D_ST

32'h0000588C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC_1D_SZ

32'h00005890

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC_2D_ST

32'h00005894

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC_2D_SZ

32'h00005898

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 2D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC_3D_ST

32'h0000589C

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC_3D_SZ

32'h000058A0

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 3D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC_4D_ST

32'h000058A4

Range

Field

Reset

Description

[23:0]

step

0x1

Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_DESC_4D_SZ

32'h000058A8

Range

Field

Reset

Description

[23:0]

size

0x1

Number of steps per 4D dimension Value of 0 is invalid and treated as 1

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_START

32'h000058AC

Range

Field

Reset

Description

[0:0]

EN

0x0

Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy)

Access

Register

Address

Description

(W-)

v64bDhub_dHub0_Cmd4ND15_CLEAR

32'h000058B0

Range

Field

Reset

Description

[0:0]

EN

0x0

Write anything to reset the 4ND engine.

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_Cmd4ND15_FLEXA

32'h000058B4

Range

Field

Reset

Description

[7:0]

STREAM_ID

0x0

The FLEXA stream ID

[9:8]

CID

0x0

Consumer ID

[10:10]

ENDOFSTR

0x0

When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine

[11:11]

WITHOUT_WAIT

0x0

Request for a segment without waiting for data consumer (or producer)

[13:12]

TIMEOUT

0x0

Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold;

[14:14]

END

0x0

Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”.

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_Cmd4ND15_FLEXA_INTR_STA

32'h000058B8

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[5:3]

outsync_01

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

[8:6]

outsync_10

0x0

Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync

Access

Register

Address

Description

(P)

v64bDhub_dHub0_Cmd4ND15_FLEXA_INTR_MSK

32'h000058BC

Range

Field

Reset

Description

[2:0]

outsync_00

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00

[5:3]

outsync_01

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01

[8:6]

outsync_10

0x0

Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND

Access

Register

Address

Description

(R-)

v64bDhub_dHub0_BUSY

32'h000058C0

Range

Field

Reset

Description

[15:0]

ST

Per channel status 0: no ongoing command is being processed 1: channel controller is busy

Access

Register

Address

Description

(RW)

v64bDhub_dHub0_mem

32'h00005900

end dHubReg2D Internal memory

Range

Field

Reset

Description

[31:0]

Memory

Memory